HES-SO Valais : since 2001
- Lecturer in Integrated Electronics and Embedded System
- Project Manager and technical responsible for several HES-SO, CTI and industrial projects
Alcatel space Switzerland: 1993-2001
- 2000-2001
Integrated electronics engineering manager: supervision of ASICs and FPGAs development (ATV TCU, PEMS, MMD)
Equipment responsible: Technical management of the control unit (CU) and memory boards (MEM) of the data compression and storage unit (DCSU). - 1999-2000
Responsible for the specification and digital HW design of the PTMB board of PTDCU (Platinum Data Collection Unit) equipment for the Large Space Simulator of ESTEC. - 1998-1999
Responsible for the specification and hardware design of the space qualified CCE ASIC of IASI instrument (METOP). - 1997-1998
Responsible for the hardware design of the space qualified CASTOR ASIC (Sparc co-processor) of TOPSTAR 3000 equipment. - 1997
Responsible for the hardware design of the space qualified ARMS FPGA (Advance respiratory monitoring sequencer) of ARMS equipment. - 1996-1997
Responsible for the hardware design of the space qualified IFD (Decentralized IinterFace) ASIC of COF PDU (COlumbus Facility) equipment. - 1996
Responsible for the hardware design of the space qualified TTT (Telemetry, telecommand, time) ASIC of LVDE project (Helios 2). - 1995-1996
Responsible for the hardware design of the space qualified Controller ASIC of MDU equipment of MSG (Meteosat second generation) satellite. - 1994-1995
Responsible for the hardware design of the RS232 and RS422 commutation drawer used in the telemetry system of ARIANE5. - 1993-1994
Responsible for the hardware design of the EGSE of MERIS instrument mounted on ENVISAT satellite.
